1 ? fn4316.10 hin232a high speed +5v powered rs-232 transmitters/receivers the hin232a high-speed rs-232 transmitter/receiver interface circuit meets all ela high-speed rs-232e and v.28 specifications, and is part icularly suited for those applications where 12v is not available. they require a single +5v power supply and feature onboard charge pump voltage converters which gener ate +10v and -10v supplies from the 5v supply. the drivers feature true ttl/cm os input compatibility, slew rate-limited output, and 300 ? power-off source impedance. the receivers can handle up to 30v input, and have a 3k ? to 7k ? input impedance. the re ceivers also feature hysteresis to greatly improve noise rejection. features ? meets all rs-232e and v.28 specifications ? requires only 0.1 f or greater exte rnal capacitors ? high data rate. . . . . . . . . . . . . . . . . . . . . . . . . . 230kbit/s ? requires only single +5v power supply ? onboard voltage doubler/inverter ? low power consumption (typ) . . . . . . . . . . . . . . . . . 5ma ? multiple drivers - 10v output swing for +5v lnput -300 ? power-off source impedance - output current limiting - ttl/cmos compatible ? multiple receivers - 30v input voltage range -3k ? to 7k ? input impedance - 0.5v hysteresis to improve noise rejection applications ? any system requiring high-speed rs-232 communication ports - computer - portable, mainframe, laptop - peripheral - printers and terminals - instrumentation, ups - modems ordering information part no. temp. range ( o c) package pkg. dwg. # hin232acb 0 to 70 16 ld soic m16.3 hin232acb-t 0 to 70 16 ld soic tape and reel m16.3 hin232acbn 0 to 70 16 ld soic (n) m16.15 hin232acbn-t 0 to 70 16 ld soic (n) tape and reel m16.15 hin232acp 0 to 70 16 ld pdip e16.3 selection table part number power supply voltage number of rs-232 drivers number of rs-232 receivers number of 0.1 f external capacitors low power shutdown/ttl three- state number of receivers active in shutdown hin232a +5v 2 2 4 capacitors no/no 0 data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved
2 pinout hin232a (pdip, soic) top view pin descriptions pin function v cc power supply input 5v 10%. v+ internally generated posit ive supply (+10v nominal). v- internally generated negative supply (-10v nominal). gnd ground lead. connect to 0v. c1+ external capacitor (+ termi nal) is connected to this lead. c1- external capacitor (- terminal) is connected to this lead. c2+ external capacitor (+ termi nal) is connected to this lead. c2- external capacitor (- terminal) is connected to this lead. t in transmitter inputs. these leads accept ttl/cmos levels. an internal 400k ? pull-up resistor to v cc is connected to each lead. t out transmitter outputs. these are rs-232 levels (nominally 10v). r in receiver inputs. these inputs accept rs-232 input levels. an internal 5k ? pull-down resistor to g nd is connected to each input. r out receiver outputs. these are ttl/cmos levels. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd v- v cc +5v 2 v+ 16 t1 out t2 out t1 in t2 in t1 t2 11 10 14 7 +5v 400k ? +5v 400k ? r1 out r1 in r1 13 12 5k ? r2 out r2 in r2 8 9 5k ? +10v to -10v voltage inverter 0.1 f 6 v- c2+ c2- + 0.1 f 4 5 +5v to 10v voltage inverter c1+ c1- + 0.1 f 1 3 + 0.1 f + gnd 15 hin232a
3 absolute maximum rati ngs thermal information v cc to ground. . . . . . . . . . . . . . . . . . . . . . (gnd -0.3v) 4 detailed description the hin232a is a high-speed rs-232 transmitter/receiver that is powered by a single +5v power supply, features low power consumption, and meets all ela rs232c and v.28 specifications. the circuit is di vided into three sections: the charge pump, transmitter, and receiver. charge pump an equivalent circuit of the charge pump is illustrated in figure 3. the charge pump contains two sections: the voltage doubler and the voltage inverter. each section is driven by a two phase, internally generated clock to generate +10v and -10v. the nominal clock frequency is 125khz. during phase one of the clock, capacitor c1 is charged to v cc . during phase two, the voltage on c1 is added to v cc , producing a signal across c3 equal to twice v cc . during phase two, c2 is also charged to 2v cc , and then during phase one, it is inverted with respect to ground to produce a signal across c4 equal to -2v cc . the charge pump accepts input voltages up to 5.5v. the output impedance of the voltage doubler section (v+) is approximately 200 ? , and the output impedance of the voltage inverter section (v-) is approximately 450 ? . a typical application uses 0.1 f capacitors for c1-c4, however, the value is not critical. increasing the values of c1 and c2 will lower the output impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, c3 and c4, lowers the ripple on the v+ and v- supplies. transmitters the transmitters are ttl/cmos compatible inverters which translate the inputs to rs-232 out puts. the input logic threshold is about 26% of v cc , or 1.3v for v cc = 5v. a logic 1 at the input results in a voltage of be tween -5v and v- at the output, and a logic 0 results in a voltage between +5v and (v+ -0.6v). each transmitter input has an internal 400k ? pullup resistor so any unused input can be left unconnected and its output remains in its low state. the output voltage swing meets the rs-232c specifications of 5v minimum with the worst case conditions of: all transmitters driving 3k ? minimum load test circuits (hin232a) figure 1. general test circuit figure 2. power-off source resistance configuration 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd +4.5v to +5.5v input 3k ? t1 output rs-232 30v input ttl/cmos output ttl/cmos input ttl/cmos input ttl/cmos output + - 0.1 f c3 + - 0.1 f c1 + - 0.1 f c2 + - 0.1 f c4 3k ? output rs-232 30v input t2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd t2 out t1 out v in = 2v a r out = v in /i + - c1 + - c3 + - c2 + - c4 s1 s2 s5 s6 s3 s4 s7 s8 v cc gnd rc oscillator v cc gnd v+ = 2v cc gnd v- = - (v+) c1+ c1- c2- c2+ voltage inverter voltage doubler figure 3. charge pump hin232a
5 impedance, v cc = 4.5v, and maximum allowable operating temperature. the transmitters have an internally limited output slew rate which is less than 30v/ s. the outputs are short circuit protected and can be shor ted to ground indefinitely. the powered down output impedance is a minimum of 300 ? with 2v applied to the outputs and v cc = 0v. receivers the receiver inputs accept up to 30v while presenting the required 3k ? to 7k ? input impedance even if the power is off (v cc = 0v). the receivers have a typical input threshold of 1.3v which is within the 3v limits, known as the transition region, of the rs-232 specificat ions. the receiver output is 0v to v cc . the output will be low whenever the input is greater than 2.4v and high whenever the input is floating or driven between +0.8v and -30v. t he receivers feature 0.5v hysteresis (except during shutdow n) to improve noise rejection. application information the hin232a may be used for all rs-232 data terminal and communication links. it is partic ularly useful in applications where 12v power supplies are not available for conventional rs-232 interface circuits. the applications presented represent typical interface configurations. a simple duplex rs-232 port with cts/rts handshaking is illustrated in figure 7. fixed output signals such as dtr (data terminal ready) and dsrs (data signaling rate select) is generated by driving them through a 5k ? resistor connected to v+. in applications requiring four rs-232 inputs and outputs (figure 8), note that each circuit requires two charge pump capacitors (c1 and c2) but can share common reservoir capacitors (c3 and c4). t he benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of t he charge pump source impedance which effectively increases the outp ut swing of the transmitters. t out v- < v tout < v+ 300 ? 400k ? t xin gnd < t xin < v cc v- v+ v cc figure 4. transmitter r out gnd < v rout < v cc 5k ? r xin -30v < r xin < +30v gnd v cc figure 5. receiver t in v oh v ol t plh t phl average propagation delay = t phl + t plh 2 or r in t out or r out figure 6. propagation delay definition - + - + - + ctr (20) data terminal ready dsrs (24) data signaling rate rs-232 inputs and outputs td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send signal ground (7) 15 8 13 7 14 16 - + 6 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin232a c1 0.1 f c2 0.1 f td rts rd cts select +5v inputs outputs ttl/cmos figure 7. simple duplex rs-232 port with cts/rts handshaking hin232a
6 - + rs-232 inputs and outputs dtr (20) data terminal ready dsrs (24) data signaling rate select dcd (8) data carrier detect r1 (22) ring indicator signal ground (7) 15 8 13 7 14 2 - + 4 r2 r1 t2 t1 9 12 10 11 3 1 hin232a c1 0.1 f dtr dsrs dcd r1 +5v inputs outputs ttl/cmos - + - + td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send 8 13 7 14 15 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin232a c1 0.1 f c2 0.1 f td rts rd cts inputs outputs ttl/cmos - + 5 c2 0.1 f 16 c3 0.2 f 6 2 6 v- v+ - + c4 0.2 f 16 v cc v cc figure 8. combining two hin232as for 4 pairs of rs-232 inputs and outputs typical performance curves figure 9. v- supply voltage vs v cc figure 10. v+, v- output voltage vs load 12 10 8 6 4 2 0 3.5 4.0 4.5 6.0 v cc v- supply voltage (v) 5.0 5.5 3.0 0.1 f 35 |i load | (ma) v+ (v cc = 4v) v+ (v cc = 5v) v- (v cc = 5v) v- (v cc = 4v) t a = 25 o c transmitter outputs open circuit 30 25 20 15 10 5 0 supply voltage (v) 0 12 10 8 6 4 2 hin232a
7 die characteristics die dimensions 160 mils x 140 mils metallization type: al thickness: 10k ? 1k ? substrate potential v+ passivation type: nitride over silox nitride thickness: 8k ? silox thickness: 7k ? transistor count 238 process cmos metal gate hin232a
8 hin232a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
9 hin232a small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93
10 all intersil products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at website www.inte rsil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by int ersil is believed to be accurate and reliable. how- ever, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other r ights of third parties whic h may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com hin232a small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 02/02
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